From 473106cc71b04ced9a24bbfd7624521dc0656f7c Mon Sep 17 00:00:00 2001
From: Drahoslav <drahoslav@yo2.cz>
Date: Fri, 5 Oct 2018 21:48:50 +0200
Subject: [PATCH] Add clockmode and cspolarity SPI settings

---
 spi.go | 36 +++++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/spi.go b/spi.go
index 03368cd..bb2c4ab 100644
--- a/spi.go
+++ b/spi.go
@@ -68,7 +68,7 @@ func SpiSpeed(speed int) {
 
 // Select chip, one of 0, 1, 2
 // for selecting slave on CE0, CE1, or CE2 pin
-func SpiChipSelect(chip int) {
+func SpiChipSelect(chip uint8) {
 	const csMask = 3 // chip select has 2 bits
 
 	cs := uint32(chip & csMask)
@@ -76,6 +76,40 @@ func SpiChipSelect(chip int) {
 	spiMem[csReg] = spiMem[csReg]&^csMask | cs
 }
 
+// Sets polarity (0/1) of active chip select
+// default active=0
+func SpiChipSelectPolarity(chip uint8, polarity uint8) {
+	if chip > 2 {
+		return
+	}
+	cspol := uint32(1 << (21 + chip)) // bit 21, 22 or 23 depending on chip
+
+	if polarity == 0 { // chip select is active low
+		spiMem[csReg] &^= cspol
+	} else { // chip select is active hight
+		spiMem[csReg] |= cspol
+	}
+}
+
+// Set polarity (0/1) and phase (0/1) of spi clock
+// default polarity=0; phase=0
+func SpiMode(polarity uint8, phase uint8) {
+	const cpol = 1 << 3
+	const cpha = 1 << 2
+
+	if polarity == 0 { // Rest state of clock = low
+		spiMem[csReg] &^= cpol
+	} else { // Rest state of clock = high
+		spiMem[csReg] |= cpol
+	}
+
+	if phase == 0 { // First SCLK transition at middle of data bit
+		spiMem[csReg] &^= cpha
+	} else { // First SCLK transition at beginning of data bit
+		spiMem[csReg] |= cpha
+	}
+}
+
 // SpiTransmit takes one or more bytes and send them to slave.
 //
 // Data received from slave are ignored.