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https://github.com/stianeikeland/go-rpio.git
synced 2025-01-23 02:31:05 +01:00
Do minor renaming
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parent
aae3fc6504
commit
b7b1bd8b81
38
rpio.go
38
rpio.go
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@ -194,7 +194,7 @@ func (pin Pin) PullOff() {
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func PinMode(pin Pin, mode Mode) {
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func PinMode(pin Pin, mode Mode) {
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// Pin fsel register, 0 or 1 depending on bank
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// Pin fsel register, 0 or 1 depending on bank
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fsel := uint8(pin) / 10
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fselReg := uint8(pin) / 10
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shift := (uint8(pin) % 10) * 3
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shift := (uint8(pin) % 10) * 3
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f := uint32(0)
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f := uint32(0)
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@ -216,7 +216,7 @@ func PinMode(pin Pin, mode Mode) {
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return
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return
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}
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}
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}
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}
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gpioMem[fsel] = (gpioMem[fsel] &^ (pinMask << shift)) | (f << shift)
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gpioMem[fselReg] = (gpioMem[fselReg] &^ (pinMask << shift)) | (f << shift)
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}
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}
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// WritePin sets a given pin High or Low
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// WritePin sets a given pin High or Low
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@ -296,11 +296,11 @@ func PullMode(pin Pin, pull Pull) {
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// Set clock speed for given pin
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// Set clock speed for given pin
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//
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//
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// freq should be in range 4688 - 19.2MHz to prevent unexpected behavior
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// freq should be in range 4688Hz - 19.2MHz to prevent unexpected behavior
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// (for smaller frequencies implement custom software clock using output pin and sleep)
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// (for smaller frequencies implement custom software clock using output pin and sleep)
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//
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//
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// Note that some pins share the same clock source that means
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// Note that some pins share the same clock source, it means that
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// that changing frequency for one pin will change it also for all pins within a group
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// changing frequency for one pin will change it also for all pins within a group
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// The groups are: clk0 (4, 20, 32, 34), clk1 (5, 21, 42, 43) and clk2 (6 and 43)
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// The groups are: clk0 (4, 20, 32, 34), clk1 (5, 21, 42, 43) and clk2 (6 and 43)
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func SetClock(pin Pin, freq int) {
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func SetClock(pin Pin, freq int) {
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const source = 19200000 // oscilator frequency
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const source = 19200000 // oscilator frequency
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@ -312,18 +312,18 @@ func SetClock(pin Pin, freq int) {
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divi &= maxUint12
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divi &= maxUint12
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divf &= maxUint12
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divf &= maxUint12
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clkCtl := 0x70
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clkCtlReg := 0x70
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clkDiv := 0x74
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clkDivReg := 0x74
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switch pin {
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switch pin {
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case 4, 20, 32, 34: // clk0
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case 4, 20, 32, 34: // clk0
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clkCtl += 0
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clkCtlReg += 0
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clkDiv += 0
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clkDivReg += 0
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case 5, 21, 42, 44: // clk1
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case 5, 21, 42, 44: // clk1
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clkCtl += 8
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clkCtlReg += 8
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clkDiv += 8
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clkDivReg += 8
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case 6, 43: // clk2
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case 6, 43: // clk2
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clkCtl += 16
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clkCtlReg += 16
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clkDiv += 16
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clkDivReg += 16
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default:
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default:
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return
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return
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}
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}
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@ -336,11 +336,11 @@ func SetClock(pin Pin, freq int) {
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const enab = 0x10
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const enab = 0x10
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const src = 0x01 // oscilator
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const src = 0x01 // oscilator
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clkMem[clkCtl] = PASSWORD | src // stop gpio clock
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clkMem[clkCtlReg] = PASSWORD | src // stop gpio clock
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for clkMem[clkCtl] & busy != 0 {} // ... and wait
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for clkMem[clkCtlReg] & busy != 0 {} // ... and wait
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clkMem[clkDiv] = PASSWORD | (divi << 12) | divf // Set dividers
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clkMem[clkDivReg] = PASSWORD | (divi << 12) | divf // set dividers
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clkMem[clkCtl] = PASSWORD | enab | src // Start Clock
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clkMem[clkCtlReg] = PASSWORD | enab | src // start clock
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}
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}
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@ -364,13 +364,13 @@ func Open() (err error) {
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defer memlock.Unlock()
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defer memlock.Unlock()
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// Memory map GPIO registers to slice
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// Memory map GPIO registers to slice
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gpioMem, gpioMem8, err = memMap(file.Fd(), base + gpioOffset)
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gpioMem, gpioMem8, err = memMap(file.Fd(), gpioBase)
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if err != nil {
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if err != nil {
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return
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return
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}
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}
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// Memory map clock reisters to slice
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// Memory map clock reisters to slice
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clkMem, clkMem8, err = memMap(file.Fd(), base + clkOffset)
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clkMem, clkMem8, err = memMap(file.Fd(), clkBase)
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if err != nil {
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if err != nil {
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return
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return
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}
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}
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